Phase-locked loop circuits have been used for many years for the purpose of generating a signal in a preferred phase relationship with another signal. Prior art phase-locked loop circuits are exemplified in U.S. Pat. Nos. 4,724,402 in the name of Karl Ireland granted Feb. 9, 1988, 3,931,585 in the name of Barker et al. granted Jan. 6, 1976 and in 4,748,644 in the name of Robert T. Silver et al. granted May 31, 1988. In a telephony system, it is often required to have a local clock synchronized in a preferred phase relationship to a primary master clock provided by a larger, often remote, network. For example, in U.S. Pat. No. 4,519,071 for Phase-Locked Loop and Clock Circuit for a Line Switch, issued May 21, 1985 to Miller, a phase-locked loop circuit permits clock synchronism with any one of a number of PCM lines.
In order for a receiver to receive and capture data referenced to a transmitter's clock signal, it is necessary for the receiver to have a clock signal which is synchronized or phase-aligned to the same clock signal. Therefore, phase-locked loop circuits are often used in the clock circuits of data receivers for the purpose of generating a local clock signal phase-aligned with an incoming reference signal. The phase-locked loop (PLL) circuit within the receiver can adjust its local clock signal frequency to a multiple of the reference signal frequency thereby phase aligning the two signals together. The phase relationship between the reference signal and the local clock signal is then referred to as being locked and the receiver may receive synchronous data.
A digital PLL clock circuit usually comprises a phase detector for measuring the phase relationship between the reference signal and the local signal, a microprocessor, a digital to analog (D/A) converter, and a variable controlled oscillator for responding to the measured phase relationship. Phase detectors are commonly realized in a hardware circuit comprising a counter for counting a number of clock cycles between the reference signal and the feedback local clock signal and a register for storing the counted number of clock cycles representing the measured phase relationship therebetween. The counter is usually incremented with a signal having a frequency many times higher than the frequency of the incoming reference signal and typically the local clock signal or a multiple thereof is used to increment the counter. Due to the asynchronous relationship between the signal used for incrementing the counter and the signal used for sampling the counted value, jitter may appear on the local clock signal with respect to the reference signal. The amount of jitter present on most systems is directly proportional to the period of the signal used for incrementing the counter. In effect, there is a window within which the register is loaded with the counted value, the window being as wide as the period of the signal incrementing the counter. Periodically, the microprocessor updates the counted value with a new counted value. One of the functions of the microprocessor is to provide the D/A converter with a digital value which is a function of the most recently sampled counted value provided by the phase detector. This digital value may be an adjusted value representing the difference between the expected phase offset and the measured phase offset. Typically, when the expected phase offset equals the measured phase offset, the microprocessor does not vary the digital value. In essence, if the D/A converter is providing the oscillator with an analog voltage which is stabilizing the output signal such that the sampled value remains constant, the microprocessor does not vary the digital value. However, the amount of jitter present is proportional to the sampling window size. Thus, it is desirable that the window be as small as possible so as to minimize the amount of jitter that appears on the local clock signal and thus to provide a more stable local clock signal.
One apparently expeditious method to reduce the sampling window size is to increase the frequency with which the counter is incremented, by providing the counter with a stable high frequency signal. However, since PLL circuits typically feed back the output signal to provide local clock signals, the provision of high enough frequencies to obtain a nearly jitterless phase-locked output signal using conventional controllable oscillators is not practicable. For example, a 500 MHz oscillator would be required to achieve a two nanosecond jitter figure.